Substrate patterning techniques combining advanced lithographic processing and material deposition methods enable the fabrication of structures on substrate surfaces having well defined physical dimensions ranging from 10s of nanometers to 1000s of microns. These material processing methods are compatible with a wide range of substrate and deposition materials, including many dielectric, semiconducting and conducting materials. Given the high degree of precision and versatility provided by these methods, advanced substrate patterning techniques provide a robust fabrication platform for accessing a wide range of useful functional devices. These techniques currently play a central role in most semiconductor based technologies including, but not limited to, the manufacture of dense integrated circuits, memory devices and microelectronic devices. Furthermore, advanced substrate patterning techniques also provide a fabrication pathway for making nanometer and/or micron scale structures comprising elements in micro- and nano-electromechanical (MEMS & NEMS) and micro- and nanofluidic systems.
Recent developments in lithographic processing, including deep ultraviolet photolithography, electron beam writing and X-ray lithography methods, continue to extend the applicability of these techniques for generating patterns of smaller and smaller structures on substrate surfaces. Such advances in lithographic processing make it possible to generate very high aspect ratio recessed structures (>5:1 depth:width) having nanometer and micron sized dimensions. Such high aspect ratio structures have the potential to support densely packed device elements for (in) the next generation of microelectronic and nanoelectronic systems. Useful device elements fabricated using this method include electrical insulators (when the recessed structure is filled or coated with one or more insulators), or electrically conductive/semiconducting layers/superconducting (when the recessed structure is filled or coated with one or more conductors, semiconductors or super conductors). As device dimensions are reduced, however, significant challenges arise in filling or coating such high aspect ratio nanometer and micron size structures using conventional deposition methods. These challenges constitute a barrier to achieving the desired reduction of device dimensions (e.g. <65 nanometer) in ultra-large scale integrated circuit (ULSI) architecture and the multilevel metallization therein.
To fabricate the components of an electrical device, a selected material or combination of materials is often deposited into recessed features, such as trenches or vias, patterned into a substrate surface that spatially defines and organizes the various elements of the device. Deposition is commonly accomplished by exposure of the feature to a gas (or combination of gases) that condenses on or reacts on or with surfaces of the feature, thereby generating deposited layers that coat or fill the recessed feature with a material having selected properties. Important to providing device components exhibiting good electrical, mechanical optical and/or other properties, is the ability to fill or coat the recessed features in a continuous and conformal manner. For example, material deposition methods are preferred that form a conformal thin film layer in the recessed feature or that completely fill the feature without voids or gaps in the bulk of the deposited material or between the deposit and surfaces of the recessed features. Such voids and gaps are undesirable because they affect the electrical properties of the deposited layer, such as inductance, resistivity and/or capacitance, thereby, potentially degrading overall device performance and undermining device uniformity. Further, voids and gaps in the bulk of the deposit or between the deposit and surfaces of the recessed feature compromise the overall mechanical integrity of the processed structure.
A common problem encountered in coating or filling a recessed feature, such as a trench or via, using conventional deposition methods is that the deposition rate near the opening and the bottom of the feature is often significantly larger than the deposition rate onto the sides of the feature. This anisotropy arises from efficient supply of the deposition material to the surfaces near the opening and bottom surface in line-of-sight of the source of deposition gas. As a result of enhanced deposition to the regions of the feature near the opening, flux anisotropy of deposition gas can lead to formation of an overhang proximate to the opening that prematurely seals the opening of the feature. Sealing (or “pinching off”) of the opening prevents further deposition, thereby leaving undesirable voids or gaps in the lower regions of the recessed feature.
For high aspect ratio features (e.g. aspect ratios >5:1), the flux anisotropy of deposition gas can be so severe that virtually no material is deposited on the side walls of the recessed feature, particularly in the region of the side walls near the bottom of the feature. This problem is further exacerbated when the high aspect ratio feature being processed has small physical dimensions, such as having a width less than abut 0.1 microns, and when the deposition material has a large sticking coefficient with respect to uptake by the surface of the recessed feature. The shape of the high aspect ratio features may also contribute to an increased likelihood of void or gap formation during filling or coating. Reentrant features, such as a narrowing at the opening of the feature or widening at bottom of a feature, often enhances pinch-off problems during the processing of high aspect ratio features.
To address these challenges a number of processes have been developed for coating or filling high aspect ratio recessed features. While at least in part addressing the some of the problems with processing high aspect ratio features, these techniques are not universally compatible with all types of deposition materials, substrates and recessed feature geometries. In addition, each technique presents its own set of drawbacks that limit adoption and implementation of this technology.
Physical vapor deposition (PVD) encompasses a gamut of techniques including evaporation, sputtering and variants thereof. Due to the near-unity sticking coefficient of the arriving flux in most PVD coating applications, the ability of PVD processes to coat high aspect ratio features uniformly is severely limited. Modified PVD processes, however, such as collimated sputtering and ionized PVD have been demonstrated to provide some limited success in coating and filling moderate aspect ratio (≦5:1) features. (See, S. M. Rossnagel, J. Vac. Sci. Technol. B 16 (1998) 2585).
Conventional thermal and plasma based chemical vapor deposition (CVD) processes typically perform well for moderate to low aspect ratio (≦5:1) structures. The success of these processes for coating higher aspect ratio feature is largely dependent on operating in a regime in which the reactive species has a relatively low sticking coefficient. (See, M. M. Islamraja, M. A. Cappelli, J. P. McVittie, K. C. Saraswat, J. Appl. Phys. 70 (1991) 7137; and H. C. Wulu, K. C. Saraswat, J. P. Mcvittie, J. Electrochem. Soc. 138 (1991) 1831.).
A modified approach, high density plasma (HDP) CVD and variants, employs physical erosion (sputtering) of the deposited material from high energy ions to remove material from the exposed surfaces, including the trench opening. (See, S. V. Nguyen, IBM J. Res. Dev. 43 (1999)109; and D. R. Cote, S. V. Nguyen, A. K. Stamper, D. S. Armbrust, D. Tobben, R. A. Conti, G. Y. Lee, IBM J. Res. Dev. 43 (1999) 5, K. Takenaka, M. Kita, T. Kinoshita, K. Koga, M. Shirantani, Y. Watanabe, J. Vac. Sci. Technol. A 22 (2004), 1903). The flux of high energy ions does not impinge on the lower side walls of the trench, hence the film grows at a greater net rate in lower regions of the trench. Film and substrate damage from high energy ions, however, can be a severe limitation in this process.
Another approach is selective deposition by CVD, which is based on the inability of the precursor to nucleate a film on one substrate material compared to another. This approach has been utilized to selectively grow film on recesses in a substrate. The CVD of tungsten (W) and of group III-V semiconductors from their halogen based precursors are examples in which films nucleate on a semiconductor substrate but not on a mask material such as SiO2. (See, T. F. Kuech, M. S. Goorsky, M. A. Tischler, A. Palevski, P. Solomon, R. Potemski, C. S. Tsai, J. A. Lebens, K. J. Vahala, J. Cryst. Growth 107 (1991) 116; and K. C. Saraswat, S. Swirhun, J. P. McVittie, J. Electrochem. Soc. 131 (1984) C86). A nucleation layer at the bottom of a trench or via can afford a bottom-up fill as demonstrated for AL-CVD. (See, L. Y. Chen, T. Guo, R. C. Mosley, F. Chen, Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug, U.S. Pat. No. 6,537,905, Applied Materials Inc., 2003). Disadvantages of these techniques include the need for intermediate photolithographic steps to define a mask layer, and the need for mechanical polishing to remove unwanted seed layer.
Atomic Layer Deposition (ALD) is a technique with proven capability to coat aspect ratios exceeding 100. (See, R. G. Gordon, Abstr. Pap. Am. Chem. Soc. 227 (2004) U553; J. E. Crowell, J. Vac. Sci. Technol. A 21 (2003) S88; H. Kim, J. Vac. Sci. Technol. B 21 (2003) 2231; B. S. Lim, A. Rahtu, R. G. Gordon, Nat. Mater. 2 (2003) 749). The ALD process works by sequential exposure of the substrate to two different reactant gases under the special condition that the surface reactions during each exposure are self-limiting. The film typically grows at a very slow rate (e.g. a fraction of a monolayer per cycle), and, therefore, the cycle time is limited by the rate at which each reactant can be filled into and emptied from the growth chamber (or the lower portion of the recessed structure, whichever is longer). The disadvantage of this technique is the slow growth rate of the deposited film.
Electrochemical Deposition (ECD) is a well established and popular technique for coating surfaces and for filling deep features. This technique is commonly used to produce bottom-up growth of copper in trenches on ULSI circuits: differential plating kinetics are used to obtain “superconformal” or “super-filled” features. (See, P. M. Vereecken, R. A. Binstead, H. Deligianni, P. C. Andricacos, IBM J. Res. Dev. 49 (2005) 3). The differential plating kinetics are generated by using specific additives that segregate to the trench top or bottom and serve as either leveler (for differential inhibition of growth) or catalyst (for differential acceleration of growth). The net effect of ECD methods is a higher growth rate at the trench bottom.
Bottom-up Copper CVD extends the idea in electrochemical deposition to CVD approaches. In copper CVD from hexafluoroacetylacetonate-copper-vinyltrimethylsilane, iodine is added as a catalytic-surfactant to enable a bottom-up fill. (See, K. C. Shim, H. B. Lee, O. K. Kwon, H. S. Park, W. Koh, S. W. Kang, J. Electrochem. Soc. 149 (2002) G109). In this method, iodine is provided as a growth promoter and has a concentration that rises inside the feature as the deposition proceeds.
Bottom-up growth was reported by Heitzinger et al. in the specific system of polysilicon deposition from silane (the CVD precursor) when arsine was added to the process gas. (See, C. Heitzinger, W. Pyka, N. Tamaoki, T. Takase, T. Ohmine, S. Selberherr, IEEE Tran. Comput. Aided. Design. 22 (2003) 285.). In this method, arsine acts as a growth suppressor and is also incorporated into the deposition layer. A high process temperature (700° C.) is required to ensure a high reaction rate for arsine. The authors modeled their trench coverage on the basis of depleting arsine concentration in the trench and conclude that the experimental conditions employed result in operation in the time limit domain. (See, page 291, paragraph 3). The time limit stems from the fact that the suppressor is re-emitted from the film surface at some rate and ultimately will diffuse to the bottom of the trench, despite that fact that it has a higher sticking coefficient and lower concentration with respect to the precursor. In time limit domain, the bottom-up growth only takes place before the suppressor arrives at the bottom of the via by diffusion. After that, the suppressor concentration saturates from top to bottom and yields equal growth rates at all locations inside the via. A significant disadvantage of the time domain techniques described in Heitzinger et al. is that coating/filling larger structures requires a longer time to build up the appropriate layer thickness; and, thus, the time-limit bottom-up growth will not work because the suppressor will reach the bottom of the via before the structure is filled. Moreover, the time delay in these systems is very short (e.g. 54.25 s in FIG. 8 and 23.92 s in FIG. 9 of Heitzinger et al.) and it is difficult to control such a short growth time during processing.
It will be appreciated from the foregoing that there is currently a need in the art for methods of conformally or superconformally coating and uniformly filling features on substrates. Specifically, processing methods are needed that are capable of filling and coating high aspect ratio recessed features having small dimensions (e,g. 10 nanometers to 1000 microns).